HC4GX15 Datasheet, PDF (444/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–180
Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
Figure 1–150. Examples of Illegal Transceiver Placement in (OIF) CEI PHY Interface Mode
Ch 3 ^{(OIF) CEI PHY Interface Mode with the}
low-jitter option enabled
(OIF) CEI PHY Interface Mode with the
Ch 2
low-jitter option enabled
Ch 1
Serial RapidIO
Ch 0
Serial RapidIO
(OIF) CEI PHY Interface Mode with the
Ch 3
low-jitter option enabled
(Data Rate = 5 Gbps)
(OIF) CEI PHY Interface Mode with the
Ch 2
low-jitter option enabled
(Data Rate = 5 Gbps)
(OIF) CEI PHY Interface Mode with the
Ch 1
low-jitter option enabled
(Data Rate = 6 Gbps)
(OIF) CEI PHY Interface Mode with the
Ch 0
low-jitter option enabled
(Data Rate = 6 Gbps)
Serial RapidIO Mode
The RapidIO Trade Association defines a high-performance, packet-switched
interconnect standard to pass data and control information between microprocessors,
digital signal, communications, and network processors, system memories, and
peripheral devices.
Serial RapidIO physical layer specification defines three line rates:
■ 1.25 Gbps
■ 2.5 Gbps
■ 3.125 Gbps
It also defines two link widths—single-lane (1×) and bonded four-lane (4×) at each
line rate.
HardCopy IV GX transceivers support only single-lane (1×) configuration at all three
line rates. Four 1× channels configured in Serial RapidIO mode can be instantiated to
achieve a 4× Serial RapidIO link. The four transmitter channels in this 4× Serial
RapidIO link are not bonded. The four receiver channels in this 4× Serial RapidIO link
do not have lane alignment or deskew capability.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation