HC4GX15 Datasheet, PDF (373/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
1–109
width. For example, at 3.2 Gbps data rate with a deserialization factor of 10, the
receiver PCS datapath runs at 320 MHz. The 10-bit parallel received data and status
signals at 320 MHz cannot be forwarded to the core fabric because it violates the
upper limit of 250 MHz. The byte serializer converts the 10-bit parallel received data
at 320 MHz into 20-bit parallel data at 160 MHz before forwarding to the core fabric.
1 The byte deserializer is required in configurations that exceed the core
fabric-transceiver interface clock upper frequency limit. It is optional in
configurations that do not exceed the core fabric-transceiver interface clock upper
frequency limit.
The byte deserializer operates in two modes:
■ Single-width mode
■ Double-width mode
Byte Deserializer in Single-Width Mode
In single-width mode, the byte deserializer receives 8 bit wide data from the 8B/10B
decoder or 10 bit wide data from the word aligner (if the 8B/10B decoder is disabled)
and deserializes it into 16 bit or 20 bit wide data at half the speed.
Figure 1–93 shows the byte deserializer in single-width mode.
Figure 1–93. Byte Deserializer in Single-Width Mode
datain[7:0]
or
D1 D2 D3 D4
datain[9:0]
Byte
Deserializer
D2
D4
dataout[15:0]
or
D1
D3
dataout[19:0]
/2
Receiver PCS Clock
Byte Deserializer in Double-Width Mode
In double-width mode, the byte deserializer receives 16 bit wide data from the
8B/10B decoder or 20 bit wide data from the word aligner (if the 8B/10B decoder is
disabled) and deserializes it into 32 bit or 40 bit wide data at half the speed.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3