HC4GX15 Datasheet, PDF (448/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1 The grayed out blocks shown in Figure 1–153 are not available in the CMU channels.
Therefore, the CMU channels can be configured to operate as transceiver channels in
PMA-Direct mode only.
In Basic (PMA-Direct) Mode, you can configure the transceiver channel in two main
configurations:
■ Basic PMA-Direct ×1 configuration and
■ Basic PMA-Direct ×N configuration.
You can configure the transceiver in Basic PMA-Direct ×1/ ×N mode by setting the
appropriate sub-protocol in the Which sub protocol will you be using? field. You can
select single-width or double-width by selecting Single/Double in the What is the
deserializer block width? field in the ALTGX MegaWizard Plug-In Manager.
In single-width mode, the PMA-PLD interface is 8 bit/10 bit wide; whereas in
double-width mode, the PMA-PLD interface is 16 bit/20 bit wide.
Table 1–51 shows the PLD-PMA interface widths and data rates supported in Basic
PMA-Direct ×1/×N single-width and double-width modes.
Table 1–51. Basic Deterministic Latency Mode
Basic PMA Direct ×1/×N Functional Mode
Basic PMA Direct ×1/ ×N Single-Width Mode
Basic PMA Direct ×1/ ×N Double-Width Mode
Supported Data Rate Range
at Speed Grade -3
600 Mbps to 1.28 Gbps
600 Mbps to 1.6 Gbps
1 Gbps to 2.56 Gbps
1 Gbps to 3.2 Gbps
Core Fabric
frequency (Max)
318.75 MHz
318.75 MHz
318.75 MHz
318.75 MHz
Core Fabric-PMA
Interface Width
8 bit
10 bit
16 bit
20 bit
Basic PMA-Direct x1 Configuration
You can configure a transceiver channel in this mode by setting the which protocol
will you be using? field to Basic (PMA-Direct) and the which sub protocol will you
be using? field to none. In this configuration, the Quartus II software requires one of
the two CMU PLLs within the same transceiver block to provide high-speed clocks to
the transmitter side of the channel.
Basic PMA-Direct xN Configuration
You can configure a transceiver channel in this mode by setting the which protocol
will you be using field to Basic (PMA-Direct) and the which sub protocol will you
be using field to ×N. In this mode, all the transmitter channels can receive their
high-speed clock from the CMU PLL0 from the transceiver blocks or the ATX PLL
present on the same side of the device. These clocks are provided through the ×N_Top
or ×N_Bottom clock line.
Each receiver in a receiver channel has a dedicated CDR that provides a high-speed
clock.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation