HC4GX15 Datasheet, PDF (126/668 Pages) Altera Corporation – HardCopy IV Device Handbook

8–16
Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
Differential Pin Placement Guidelines
Figure 8–17. Bit-Order and Word Boundary for One Differential Channel (Note 1)
Transmitter Channel
Operation (x8 Mode)
tx_outclock
Previous Cycle
Current Cycle
Next Cycle
tx_out X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X
MSB
LSB
Receiver Channel
Operation (x4 Mode)
rx_inclock
rx_in 3 2 1 0 X X X X X X X X X X X X
rx_outclock
rx_out [3..0]
XXXX
XXXX
XXXX
3210
Receiver Channel
Operation (x8 Mode)
rx_inclock
rx_in 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X X X X X X X X
rx_outclock
rx_out [7..0]
XXXXXXXX
XXXXXXXX
XXXX7654
3210XXXX
Note to Figure 8–17:
(1) These are only functional waveforms and are not intended to convey timing information.
For other serialization factors, use the Quartus II software tools and find the bit
position within the word. The bit positions after deserialization are listed in Table 8–5.
Table 8–5 shows the conventions for differential bit naming for eight differential
channels. The MSB and LSB positions increase with the number of channels used in a
system.
Table 8–5. LVDS Channels Supported in HardCopy IV Device Left and Right (Row) I/O Banks
Internal 8-Bit Parallel Data
Receiver Channel Number
1
2
3
4
5
6
7
8
MSB Position
7
15
23
31
39
47
55
63
LSB Position
0
8
16
24
32
40
48
56
Differential Pin Placement Guidelines
To ensure proper high-speed operation, differential pin placement guidelines have
been established. Also, the Quartus II compiler automatically verifies these guidelines
and issues an error message if they are not met.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation