HC4GX15 Datasheet, PDF (336/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
Manual Lock Mode
In automatic lock mode, the LTR/LTD controller relies on the PPM detector and the
phase relationship detector to set the CDR in LTR or LTD mode. The PPM detector
and phase relationship detector reaction times can be too long for some applications
that require faster CDR lock time. You can manually control the CDR to reduce its lock
time using the rx_locktorefclk and rx_locktodata ports. In manual lock
mode, the LTR/LTD controller sets the CDR in LTR or LTD mode depending on the
logic level on the rx_locktorefclk and rx_locktodata signals.
When the rx_locktorefclk signal is asserted high, the LTR/LTD controller forces
the CDR to lock to the reference clock. When the rx_locktodata signal is asserted
high, it forces the CDR to lock to data. When both signals are asserted, the
rx_locktodata signal takes precedence over the rx_locktorefclk signal,
forcing the CDR to lock to data.
When the rx_locktorefclk signal is asserted high, the rx_freqlocked signal
does not have any significance and is always driven low, indicating that the CDR is in
LTR mode. When the rx_locktodata signal is asserted high, the rx_freqlocked
signal is always driven high, indicating that the CDR is in LTD mode. If both signals
are de-asserted, the CDR is in automatic lock mode.
1 The Altera-recommended transceiver reset sequence varies depending on the CDR
lock mode.
Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the
high-speed serial recovered clock and deserializes it using the low-speed parallel
recovered clock. It forwards the deserialized data to the receiver PCS channel.
In single-width mode, the deserializer supports 8-bit and 10-bit deserialization
factors. In double-width mode, the deserializer supports 16-bit and 20-bit
deserialization factors.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation