HC4GX15 Datasheet, PDF (201/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy Design Center Implementation Process
2–5
Conclusion
Layout Verification
When the Timing Analysis reports that all timing requirements are met, the design
layout goes into the final stage of verification for manufacturability. The HardCopy
Design Center performs physical Design Rule Checking (DRC), antenna checking of
long traces of signals in the layout, and a comparison of layout to the design netlist,
commonly referred to as Layout Versus Schematic (LVS). These tasks guarantee that
the layout contains the exact logic represented in the place-and-route netlist and the
physical layout.
Design Signoff
The Altera HardCopy IV back-end design methodology has a thorough verification
and signoff process, guaranteeing your design’s functionality. Signoff occurs after
completing the final place-and-route netlist functional verification, layout verification
for manufacturability, and timing analysis. After achieving all three signoff points,
Altera begins the manufacturing of the HardCopy IV devices.
Conclusion
Altera’s back-end design methodology ensures that your design converts successfully
from your Stratix IV FPGA prototype to the HardCopy IV ASIC. Altera’s unique
system development methodology offers an excellent way for you to benefit from
using a Stratix IV FPGA for design prototyping and debugging, and using a
HardCopy IV ASIC for volume production.
Document Revision History
Table 2–1 shows the revision history for this chapter.
Table 2–1. Document Revision History
December 2008 1.0 Initial release.
© December 2008 Altera Corporation
HardCopy IV Device Handbook, Volume 2