HC4GX15 Datasheet, PDF (94/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 7: External Memory Interfaces in HardCopy IV Devices
HardCopy IV External Memory Interface Features
Each bank can use settings from either or both DLLs of the adjacent bank. For
example, DQS1L can use phase-shift settings from DLL1, and DQS2L can use
phase-shift settings from DLL2. Table 7–8 lists the DLL location and supported I/O
banks for HardCopy IV devices.
1 You can only have one memory interface in I/O banks with the same I/O bank
number (such as I/O banks 1A and 1C) when the leveling delay chains are used,
because there is only one leveling delay chain shared by these I/O banks.
Table 7–8. DLL Location and Supported I/O Banks
DLL
Location
Accessible I/O Banks
DLL1
DLL2
DLL3
DLL4
Top left corner
Bottom left corner
Bottom right corner
Top right corner
1A, 1C, 2A, 2C, 7A, 7B, 7C, 8A, 8B, 8C
1A, 1C, 2A, 2C, 3A, 3B, 3C, 4A, 4B, 4C
3A, 3B, 3C, 4A, 4B, 4C, 5A, 5C, 6A, 6C
5A, 5C, 6A, 6C, 7A, 7B, 7C, 8A, 8B, 8C
The reference clock for each DLL may come from the PLL output clocks or any of the
two dedicated clock input pins located in either side of the DLL. Table 7–9 and
Table 7–10 show the available DLL reference clock input resources for HardCopy IV E
devices.
Table 7–9. DLL Reference Clock Input for HC4E25W and HC4E25F Devices
DLL
DLL1
DLL2
DLL3
DLL4
CLKIN (Top/Bottom)
CLK12P, CLK13P, CLK14P, CLK15P
CLK4P, CLK5P, CLK6P, CLK7P
CLK4P, CLK5P, CLK6P, CLK7P
CLK12P, CLK13P, CLK14P, CLK15P
CLKIN (Left/Right)
CLK0P, CLK1P, CLK2P, CLK3P
CLK0P, CLK1P, CLK2P, CLK3P
CLK8P, CLK9P, CLK10P, CLK11P
CLK8P, CLK9P, CLK10P, CLK11P
PLL (Top/Bottom)
PLL_T1
PLL_B1
PLL_B1
PLL_T1
PLL (Left/Right)
PLL_L2
PLL_L2
PLL_R2
PLL_R2
Table 7–10. DLL Reference Clock Input for HC4E35L and HC4E35F Devices
DLL
CLKIN (Top/Bottom)
DLL1 CLK12P, CLK13P, CLK14P, CLK15P
DLL2 CLK4P, CLK5P, CLK6P, CLK7P
DLL3 CLK4P, CLK5P, CLK6P, CLK7P
DLL4 CLK12P, CLK13P, CLK14P, CLK15P
CLKIN (Left/Right)
CLK0P, CLK1P, CLK2P, CLK3P
CLK0P, CLK1P, CLK2P, CLK3P
CLK8P, CLK9P, CLK10P, CLK11P
CLK8P, CLK9P, CLK10P, CLK11P
PLL (Top/Bottom)
PLL_T1
PLL_B1
PLL_B2
PLL_T2
PLL (Left/Right)
PLL_L1, PLL_L2
PLL_L3, PLL_L4
PLL_R3, PLL_R4
PLL_R1, PLL_R2
Table 7–11 through Table 7–13 list the available DLL reference clock input resources
for HardCopy IV GX devices.
Table 7–11. DLL Reference Clock Input for HC4GX15LA and HC4GX25L Devices (Part 1 of 2)
DLL
CLKIN (Top/Bottom)
DLL1 CLK12P, CLK13P, CLK14P, CLK15P
DLL2 CLK4P, CLK5P, CLK6P, CLK7P
DLL3 CLK4P, CLK5P, CLK6P, CLK7P
CLKIN (Left/Right)
CLK0P, CLK1P, CLK2P, CLK3P (1)
CLK0P, CLK1P, CLK2P, CLK3P (1)
—
PLL (Top/Bottom) PLL (Left/Right)
PLL_T1
PLL_L1 (2)
PLL_B1
—
PLL_B1
—
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation