HC4GX15 Datasheet, PDF (287/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–23
CMU Channels
Figure 1–7 shows a top-level block diagram of the CMU channels in a transceiver
block.
Figure 1–7. Top-Level Diagram of CMU Channels in a Transceiver Block
HardCopy IV GX Transceiver Block
To Transmitter PMA
To Transmitter PCS
High-Speed Serial Clock
Low-Speed Parallel Clock
Local Clock
Divider
Block
Transmitter Channel 2
Transmitter Channel 3
Input Reference
Clocks
Input Reference
Clocks
CMU1 Channel
CMU0 Channel
To Transmitter PMA
To Transmitter PCS
High-Speed Serial Clock
Low-Speed Parallel Clock
Local Clock
Divider
Block
Transmitter Channel 0
Transmitter Channel 1
Note to Figure 1–7:
(1) Clocks are provided to support bonded channel functional mode.
CMU1 PLL
High-Speed Clock
CMU0 PLL
High-Speed Clock
High-Speed
SERIAL Clock (1)
Low-Speed
PARALLEL Clock (1)
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3