HC4GX15 Datasheet, PDF (364/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
Figure 1–79 shows an example of rate match FIFO deletion in the case where three
skip patterns are required to be deleted. In this example, /K28.5/ is the control
pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a
/K28.5/ control pattern followed by two /K28.0/ skip patterns. The second skip
cluster has a /K28.5/ control pattern followed by four /K28.0/ skip patterns. The rate
match FIFO deletes only one /K28.0/ skip pattern from the first skip cluster to
maintain at least one skip pattern in the cluster after deletion. Two /K28.0/ skip
patterns are deleted from the second cluster for a total of three skip patterns deletion
requirement.
Figure 1–79. Rate Match Deletion in Basic Single-Width Mode
Three Skip Patterns Deleted
First Skip Cluster
Second Skip Cluster
datain
dataout
K28.5
K28.5
K28.0
K28.0
K28.0
K28.5
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
K28.0
K28.0
rx_rmfifodatadeleted
Figure 1–80 shows an example of rate match FIFO insertion in the case where three
skip patterns are required to be inserted. In this example, /K28.5/ is the control
pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a
/K28.5/ control pattern followed by three /K28.0/ skip patterns. The second skip
cluster has a /K28.5/ control pattern followed by one /K28.0/ skip pattern. The rate
match FIFO inserts only two /K28.0/ skip patterns into the first skip cluster to
maintain a maximum of five skip patterns in the cluster after insertion. One /K28.0/
skip pattern is inserted into the second cluster for a total of three skip patterns to meet
the insertion requirement.
Figure 1–80. Rate Match Insertion in Basic Single-Width Mode
Three Skip Patterns Inserted
First Skip Cluster
Second Skip Cluster
datain
dataout
K28.5
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
K28.0
K28.5
K28.0
K28.0
K28.0
K28.0
K28.5
Dx.y
K28.0
K28.0
K28.0
Dx.y
rx_rmfifoinserted
Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the core fabric
to indicate rate match FIFO full and empty conditions.
The rate match FIFO in Basic single-width mode automatically deletes the data byte
that causes the FIFO to go full and asserts the rx_rmfifofull flag synchronous to
the subsequent data byte.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation