HC4GX15 Datasheet, PDF (411/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–147
In PCI Express (PIPE) ×8 mode configured at 5 Gbps data rate, when the PIPE
rateswitch controller sees a transition on the rateswitch signal, it sends the
pcie_gen2switch control signal to the PIPE clock switch circuitry in the CMU0 clock
divider of the master transceiver block and the receiver CDR in all eight bonded
channels to switch to the instructed signaling rate. A low-to-high transition on the
rateswitch signal initiates a Gen1 (2.5 Gbps) to Gen2 (5 Gbps) signaling rateswitch.
A high-to-low transition on the rateswitch signal initiates a Gen2 (5 Gbps) to Gen1
(2.5 Gbps) signaling rateswitch.
Table 1–40 shows the transceiver clock frequencies when switching between 2.5 Gbps
and 5 Gbps signaling rates.
Table 1–40. Transceiver Clock Frequencies Signaling Rates in PCI Express (PIPE) ×8 Mode
Transceiver Clocks
Gen1 (2.5 Gbps) to Gen 2 (5 Gbps)
Gen2 (5 Gbps) to Gen1 (2.5 Gbps)
Switch (Low-to-High Transition on the Switch (High-to-Low Transition on the
rateswitch Signal)
rateswitch Signal)
High-Speed Serial Clock
1.25 GHz to 2.5 GHz
2.5 GHz to 1.25 GHz
Low-Speed Parallel Clock
250 MHz to 500 MHz
500 MHz to 250 MHz
Serial Recovered Clock
1.25 GHz to 2.5 GHz
2.5 GHz to 1.25 GHz
Parallel Recovered Clock
250 MHz to 500 MHz
500 MHz to 250 MHz
Core Fabric-Transceiver Interface Clock
125 MHz to 250 MHz
250 MHz to 125 MHz
The PIPE clock switch circuitry in the CMU0 clock divider of the master transceiver
block performs the clock switch between 250 MHz and 500 MHz on the low-speed
parallel clock when switching between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) signaling
rates. It indicates successful completion of clock switch on the
pcie_gen2switchdone signal to the PIPE rateswitch controller. The PIPE
rateswitch controller forwards the clock switch completion status to the PIPE interface
block. The PIPE interface block communicates the clock switch completion status to
the PHY-MAC layer by asserting the pipephydonestatus signal of all eight
bonded channels for one parallel clock cycle.
Figure 1–118 shows the low-speed parallel clock switch between Gen1 (250 MHz) and
Gen2 (500 MHz) in response to the change in the logic level on the rateswitch
signal. The rateswitch completion is shown marked with a one clock cycle assertion of
the pipephydonestatus signal of all eight bonded channels.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3