HC4GX15 Datasheet, PDF (363/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–99
Receiver Channel Datapath
Figure 1–78. Rate Match Insertion in GIGE Mode
First /I2/ Ordered Set
datain
Dx.y
K28.5
D16.2
Second /I2/ Ordered Set
K28.5
D16.2
dataout
Dx.y
K28.5
D16.2
K28.5
D16.2
K28.5
D16.2
Dx.y
rx_rmfifodatainserted
Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the core fabric
to indicate rate match FIFO full and empty conditions.
In GIGE mode, the rate match FIFO does not insert or delete code groups
automatically to overcome FIFO empty and full conditions, respectively. It asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least two recovered clock cycles
to indicate rate match FIFO full and empty conditions, respectively.
1 In the case of rate match FIFO full and empty conditions, you must assert the
rx_digitalreset signal to reset the receiver PCS blocks.
Rate Match FIFO in Basic Single-Width Mode
In Basic single-width mode, the rate match FIFO is capable of compensating for up to
±300 PPM (600 PPM total) difference between the upstream transmitter and the local
receiver reference clock.
1 To enable the rate match FIFO in Basic single-width mode, the transceiver channel
must have both the transmitter and the receiver channel instantiated. You must select
the Receiver and Transmitter option in the What is the operation mode? field in the
ALTGX MegaWizard Plug-In Manager. You must also enable the 8B/10B
encoder/decoder in Basic single-width mode with rate match FIFO enabled.
Depending on your proprietary protocol implementation, you can select two 20-bit
rate match patterns in the ALTGX MegaWizard Plug-In Manager under the What is
the rate match pattern1 and What is the rate match pattern2 fields. Each of the two
programmed 20-bit rate match patterns consists of a 10-bit skip pattern and a 10-bit
control pattern. You must choose 10-bit code groups that have a neutral disparity as
the skip patterns. The rate match FIFO operation begins after the word aligner
synchronization status rx_syncstatus goes high. When the rate matcher receives
either of the two 10-bit control patterns followed by the respective 10-bit skip pattern,
it inserts or deletes the 10-bit skip pattern as necessary to avoid the rate match FIFO
from overflowing or under-running.
The rate match FIFO can delete a maximum of four skip patterns from a cluster, if
there is one skip pattern left in the cluster after deletion. The rate match FIFO can
insert a maximum of four skip patterns in a cluster, if there are no more than five skip
patterns in the cluster after insertion. Two flags, rx_rmfifodatadeleted and
rx_rmfifodatainserted, indicating rate match FIFO deletion and insertion
events, respectively, are forwarded to the core fabric.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3