HC4GX15 Datasheet, PDF (19/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV Device Family Overview
1–9
Features
Table 1–6. HardCopy IV E and Stratix IV E Package, I/O Pin Count, and LVDS Pair Count Mapping (Note 1), (2), (3), (4)
HardCopy IV E
ASIC
WF484
FF484
WF780
FF780
LF1152
FF1152
LF1517
FF1517
HC4E25
HC4E35
296, 48
—
392, 48
—
488, 56
—
—
744, 88
—
880, 88
Companion
Mapping
Stratix IV E
FPGA Prototype
F780
F780
H780
F780
H780
F1152 H1152
F1517
H1517
EP4SE230
488, 56
488, 56
—
488, 56
—
—
—
—
—
EP4SE360
—
—
488, 56
—
488, 56 744, 88
—
—
—
EP4SE530
—
—
—
—
—
—
744, 88
—
976, 112
EP4SE820
—
—
—
—
—
—
744, 88
—
976, 112
Notes to Table 1–6:
(1) The numbers in the table indicate I/O pin count, full duplex LVDS pairs.
(2) The first letter in the HardCopy IV E package name refers to the following: F–Performance-optimized flip chip package, L–Cost optimized
flip-chip package, W–Low-cost wire bond package.
(3) For the F484, F780, and F1152 packaged devices, the I/O pin counts include the eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n,
CLK8p, CLK8n, CLK10p, and CLK10n) that you can use for inputs.
(4) For the F1517 packaged device, the I/O pin count includes the eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n,
CLK10p, and CLK10n) and the eight dedicated corner PLL clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn,
PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp, and PLL_R1_CLKn) that you can use for data inputs.
Differences Between HardCopy IV and Stratix IV Devices
HardCopy IV devices have several architectural differences from Stratix IV devices.
When implementing your design and laying out your board, consider these
differences. Use this information to ensure that your design maps from the Stratix IV
FPGA to the HardCopy IV ASIC:
■ Configuration is not required for HardCopy IV devices; therefore, the following
Stratix IV features are not supported:
■ Programming modes and features such as remote update and Programmers
Object File (.pof) encryption
■ Cyclical redundancy check (CRC) for configuration error detection
■ 256-bit (AES) volatile and non-volatile security keys to protect designs
■ JTAG instructions used for configuration.
■ FPGA configuration emulation mode is not supported in HardCopy IV devices.
■ Boundary scan (BSCAN) chain length is different and varies with device density.
■ HardCopy IV devices contain up to a maximum of 20 I/O banks; Stratix IV
devices contain up to a maximum of 24 I/O.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1