HC4GX15 Datasheet, PDF (220/668 Pages) Altera Corporation – HardCopy IV Device Handbook

3–18
Chapter 3: Mapping Stratix IV Device Resources to HardCopy IV Devices
Designing with HardCopy IV I/Os
Table 3–12. Number of DQS/DQ Groups in HardCopy IV E Devices per Side (Note 1) (Part 2 of 2)
HardCopy IV E
ASIC
Package
Side
x4 (2)
x8/x9
x16/x18 x32/x36
Left
14
6
2
0
HC4E25
780-pin
FineLine BGA
Bottom
Right
17
14
8
6
2
2
0
0
Top
17
8
2
0
Left
26
12
4
0
HC4E35
1152-pin
FineLine BGA
Bottom
Right
26
26
12
12
4
4
0
0
Top
26
12
4
0
Left
26
12
4
0
HC4E35
1517-pin
FineLine BGA
Bottom
Right
38
26
18
12
8
4
4
0
Top
38
18
8
4
Notes to Table 3–12:
(1) These numbers are preliminary.
(2) Some of the DQS and DQ pins can also be used as R_UP/R_DN pins. You lose one DQS/DQ group if you use these
pins as R_UP/R_DN pins for OCT calibration. Make sure that the DQS/DQ groups that you have chosen are not also
used for OCT calibration.
f For more information about external memory interfaces, refer to the External Memory
Interfaces in HardCopy IV Devices chapter.
Mapping Stratix IV High-Speed Differential I/O Interfaces with HardCopy IV
HardCopy IV ASICs have the same dedicated circuitry as Stratix IV devices for
high-speed differential I/O support:
■ Differential I/O buffer
■ Transmitter serializer
■ Receiver deserializer
■ Data realignment
■ Dynamic phase aligner (DPA)
■ Synchronizer (FIFO buffer)
■ Analog PLLs (located on left and right sides of the device)
For high-speed differential interfaces, HardCopy IV devices support the following
differential I/O standards:
■ Low-voltage differential signaling (LVDS)
■ Mini-LVDS
■ Reduced swing differential signaling (RSDS)
■ Differential HSTL
■ Differential SSTL
HardCopy IV Device Handbook, Volume 2
© January 2010 Altera Corporation