HC4GX15 Datasheet, PDF (334/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–70
Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
Lock-to-Data Mode
The CDR must be in LTD mode to recover the clock from the incoming serial data
during normal operation. In LTD mode, the phase detector (PD) in the CDR tracks the
incoming serial data at the receiver buffer. Depending on the phase difference
between the incoming data and the CDR output clock, the PD controls the CDR
charge pump that tunes the VCO. Figure 1–56 shows active blocks when the CDR is in
LTD mode.
1 The PFD is inactive in LTD mode. The rx_pll_locked signal toggles randomly and
has no significance in LTD mode.
Figure 1–56. CDR in Lock-To-Data Mode
rx_locktorefclk
rx_locktodata
signal detect
rx_freqlocked
rx_datain
LTR/LTD
Controller
Phase ^Down
Detector Up
(PD)
Clock and Data Recovery (CDR) Unit
/2
pcie_gen2switch
High-Speed
Recovered Clock
Low-Speed
Recovered Clock
rx_cruclk /1, /2, /4
/2
Phase _Up
Frequency
Detector Down
(PFD)
Charge Pump
+
Loop Filter
V_CO
/L
/M
rx_pll_locked
Active Blocks
Inactive Blocks
After switching to LTD mode, it can take a maximum of 1 ms for the CDR to get
locked to the incoming data and produce a stable recovered clock. The actual lock
time depends on the transition density of the incoming data and the PPM difference
between the receiver input reference clock and the upstream transmitter reference
clock. The receiver PCS logic must be held in reset until the CDR produces a stable
recovered clock.
PCI Express (PIPE) Clock Switch Circuitry
The feedback path from the CDR VCO to the PD has a /2 divider that is used in PIPE
mode configured at Gen2 (5 Gbps) data rate for the dynamic switch between Gen1
(2.5 Gbps) and Gen2 (5 Gbps) signaling rates. When the PHY-MAC layer instructs a
Gen2-to-Gen1 signaling rateswitch, the /2 divider is enabled. When the PHY-MAC
layer instructs a Gen1-to-Gen2 signaling rateswitch, the /2 divider is disabled. For
more information about the PIPE signaling rateswitch, refer to “Dynamic Switch
Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rate” on page 1–138.
1 The /2 divider in the receiver CDR between the VCO and the PD is disabled in all
other functional modes.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation