HC4GX15 Datasheet, PDF (302/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–38
Chapter 1: HardCopy IV GX Transceiver Architecture
Transmitter Channel Datapath
In bonded functional modes such as XAUI, the write clock of the FIFO is clocked by
coreclkout provided by the CMU0 clock divider block. You can clock the write side
using tx_coreclk provided from the core fabric by enabling the tx_coreclk port
in the ALTGX MegaWizard Plug-In Manager. If you use this port, ensure that there is
0 PPM difference in frequency between the write and read side. The Quartus II
software requires that you provide a 0 PPM assignment in the Assignment Editor.
Input Data
In PCI Express (PIPE) functional mode, the input data comes from the PIPE interface.
In all other functional modes, the input data comes directly from the core fabric.
Output Data Destination Block
The output from the TX phase compensation FIFO is used by the byte serializer block,
8B/10B encoder, or serializer block. Table 1–5 lists the conditions under which the TX
phase compensation FIFO outputs are provided to these blocks.
Table 1–5. Output Data Destination Block for TX Phase Compensation FIFO Output Data
Byte Serializer
8B/10B Encoder
If you select:
If you select:
single-width mode and channel single-width mode and
width = 16 or 20
channel width = 8 and
8B/10B encoder enabled
If you select:
double-width mode and
channel width = 32 or 40
If you select:
double-width mode and
channel width = 16 and
8B/10B encoder enabled
Serializer
If you select:
low-latency PCS bypass mode
enabled or
single-width mode and channel
width = 8 or 10
If you select:
low-latency PCS bypass mode
enabled or
double-width mode and channel
width = 16 or 20
TX Phase Compensation FIFO Status Signal
An optional tx_phase_comp_fifo_error port is available in all functional modes
to indicate a receiver phase compensation FIFO overflow or under-run condition. The
tx_phase_comp_fifo_error signal is asserted high when the TX phase
compensation FIFO either overflows or under-runs due to any frequency PPM
difference between the FIFO read and write clocks. If the
tx_phase_comp_fifo_error flag is asserted, verify the core fabric-transceiver
interface clocking to ensure that there is 0 PPM difference between the TX phase
compensation FIFO read and write clocks.
Byte Serializer
The byte serializer divides the input datapath by two. This allows the transceiver
channel to run at higher data rates while keeping the core fabric interface frequency
within the maximum limit of 250 MHz. In single-width mode, it converts the two byte
wide datapath to a one byte wide datapath. In double-width mode, it converts the
four-byte wide datapath to a two byte wide datapath.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation