HC4GX15 Datasheet, PDF (469/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
2–11
Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration
Dynamic Reconfiguration Controller Port List
Table 2–2 describes the input control ports and output status ports of the dynamic
reconfiguration controller.
Table 2–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 1 of 9)
Port Name
Input/
Output
Description
Clock Inputs to ALTGX_RECONFIG Instance
reconfig_clk
Input
The frequency range of this clock depends on the following
transceiver channel configuration modes:
■ Receiver only (37.5 MHz to 50 MHz)
■ Receiver and Transmitter (37.5 MHz to 50 MHz)
■ Transmitter only (2.5 MHz to 50 MHz)
For more information, refer to Table 2–3 on page 2–20. By default,
the Quartus II software assigns a global clock resource to this port.
ALTGX and ALTGX_RECONFIG Interface Signals
reconfig_fromgxb
Input
reconfig_togxb[3..0]
Output
The width of this signal is determined by the value you set in the
What is the number of channels controlled by the reconfig
controller? option in the Reconfiguration settings screen.
For more information, refer to “Connecting the reconfig_fromgxb
and reconfig_togxb Ports” on page 2–40.
The width of this signal is fixed to 4 bits. It is independent of the
value you set in the What is the number of channels controlled by
the reconfig controller? option in the Reconfiguration settings
screen.
For more information, refer to “Connecting the reconfig_fromgxb
and reconfig_togxb Ports” on page 2–40.
Core Fabric and ALTGX_RECONFIG Interface Signals
write_all
Input
Assert this signal for one reconfig_clk clock cycle to initiate a
write transaction from the ALTGX_RECONFIG instance to the
ALTGX instance.
For more information, refer to “Dynamically Reconfiguring PMA
Controls” on page 2–53.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3