HC4GX15 Datasheet, PDF (349/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–85
Receiver Channel Datapath
Table 1–24. Word Aligner Options Available in Basic Single-Width and Double-Width Modes (Note 1) (Part 2 of 2)
Functional
Mode
PMA-PCS
Interface
Width
Word
Alignment
Mode
Word
Alignment
Pattern
Length
rx_enapatternalign rx_syncstatus
Sensitivity
Behavior
rx_patterndetect
Behavior
16 bit
Manual
Alignment
8, 16, and
32-bit
Rising Edge
Sensitive
Stays high after
the word aligner
aligns to the
word alignment
pattern. Goes low
on receiving a
rising edge on
rx_enapatte
rnalign until a
new word
alignment pattern
is received.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Basic
Double-width
20 bit
Bit Slip
8, 16, and
32-bit
Manual
Alignment
7, 10, and
20-bit
—
Rising Edge
Sensitive
Asserted high for
one parallel clock
cycle when the
—
word alignment
pattern appears in
the current word
boundary.
Stays high after
the word aligner
aligns to the
word alignment
pattern. Goes low
on receiving a
rising edge on
rx_enapatte
rnalign until a
new word
alignment pattern
is received.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Bit Slip
7, 10, and
20-bit
—
Asserted high for
one parallel clock
cycle when the
—
word alignment
pattern appears in
the current word
boundary.
Note to Table 1–24:
(1) For more information about word aligner operation, refer to “Word Aligner in Single-Width Mode” on page 1–74 and “Word Aligner in Double-Width
Mode” on page 1–80.
Programmable Run Length Violation Detection
The programmable run length violation circuit resides in the word aligner block and
detects consecutive 1s or 0s in the data. If the data stream exceeds the preset
maximum number of consecutive 1s or 0s, the violation is signified by the assertion of
the rx_rlv signal.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3