HC4GX15 Datasheet, PDF (42/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 5: Clock Networks and PLLs in HardCopy IV Devices
5–2
Clock Networks in HardCopy IV Devices
You can drive the 16 GCLKs in HardCopy IV devices throughout the entire device,
serving as low-skew clock sources for the core fabric and PLLs. You can also drive the
GCLKs from the device I/O elements (IOEs) and internal logic to generate global
clocks and other high fan-out control signals.
The RCLKs provide the lowest clock delay and skew for logic contained within a
single device quadrant. You can drive RCLKs from IOEs and internal logic within a
given quadrant.
The PCLKs are a collection of individual clock networks driven from the periphery of
the HardCopy IV device. Clock outputs from the dynamic phase alignment (DPA)
block, horizontal I/O pins, and internal logic can drive the PCLK networks. These
PCLKs have higher skew when compared with the GCLK and RCLK networks and
can be used instead of general purpose routing to drive signals into and out of the
HardCopy IV device.
The GCLKs, RCLKs, and PCLKs available in HardCopy IV devices are organized into
hierarchical clock structures that provide up to 192 unique clock domains (16 GCLK +
88 RCLK + 88 PCLK) across the entire device. HardCopy IV devices also allow up to
60 unique GCLK, RCLK, and PCLK clock sources (16 GCLK + 22 RCLK + 22 PCLK)
per device quadrant.
Table 5–1 lists the clock resources available in HardCopy IV devices.
Table 5–1. Clock Resources in HardCopy IV Devices
Clock Resource
Number of
Resources
Available
Source of Clock Resource
Clock input pins
32 Single-ended
(16 Differential)
CLK[0..15]p and CLK[0..15]n pins
Global clock networks
16
CLK[0..15]p/n pins, PLL clock outputs, and logic array
Regional clock networks
88
CLK[0..15]p/n pins, PLL clock outputs, and logic array
Peripheral clock networks
88 (22 per device
quadrant) (1)
DPA clock outputs, horizontal I/O pins, and logic array
GCLKs/RCLKs per quadrant
38
16 GCLKs + 22 RCLKs
GCLKs/RCLKs per device
104
16 GCLKs + 88 RCLKs
Note to Table 5–1:
(1) There are 56 PCLKs in HC4E25 and HC4GX25 devices and 88 PCLKs in HC4E35 and HC4GX35 devices. The HC4GX15 devices have 28 PCLKs.
Clocking Regions
HardCopy IV devices can implement the four different types of Stratix IV clocking
regions using GCLK and RCLK networks. These types of clocking regions include the
following:
■ Entire device clock region
■ Regional clock region
■ Dual-regional clock region
■ Sub-regional clock region
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1