HC4GX15 Datasheet, PDF (368/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–104
Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
Figure 1–86 shows the rate match FIFO empty condition in Basic double-width mode.
The rate match FIFO becomes empty after reading out the 20-bit word D5D6.
Figure 1–86. Rate Match FIFO Empty Condition in Basic Double-Width Mode
datain[19:10]
D2
D4
D6
D8
D10
D12
datain[9:0]
D1
D3
D5
D7
D9
D11
dataout[19:0]
D2
D4
D6
/K30.7/
D8
D10
dataout[9:0]
D1
D3
D5
/K30.7/
D7
D9
rx_rmfifoempty
8B/10B Decoder
Protocols such as PCI Express (PIPE), XAUI, GIGE, and Serial RapidIO require the
serial data sent over the link to be 8B/10B encoded to maintain the DC balance in the
serial data transmitted. These protocols require the receiver PCS logic to implement
an 8B/10B decoder to decode the data before forwarding it to the upper layers for
packet processing.
The HardCopy IV GX receiver channel PCS datapath implements the 8B/10B decoder
after the rate matcher. In functional modes with rate matcher enabled, the 8B/10B
decoder receives data from the rate matcher. In functional modes with rate matcher
disabled, the 8B/10B decoder receives data from the word aligner.
The 8B/10B decoder operates in two modes:
■ Single-width mode
■ Double-width mode
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation