HC4GX15 Datasheet, PDF (366/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–102
Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
The rate match FIFO can delete as many pairs of skip patterns from a cluster
necessary to avoid the rate match FIFO from overflowing. The rate match FIFO can
delete a pair of skip patterns only if the two 10-bit skip patterns appear in the same
clock cycle on the LSByte and MSByte of the 20-bit word. If the two skip patterns
appear straddled on the MSByte of a clock cycle and the LSByte of the next clock
cycle, the rate match FIFO cannot delete the pair of skip patterns. The rate match FIFO
can insert as many pairs of skip patterns into a cluster necessary to avoid the rate
match FIFO from under-running. The 10-bit skip pattern can appear on MSByte or
LSByte, or both, of the 20-bit word.
Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, indicating
rate match FIFO deletion and insertion events, respectively, are forwarded to the core
fabric.
Figure 1–83 shows an example of rate match FIFO deletion in the case where three
skip patterns are required to be deleted. In this example, /K28.5/ is the control
pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a
/K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the MSByte of a
clock cycle followed by one /K28.0/ skip pattern in the LSByte of the next clock cycle.
The rate match FIFO cannot delete the two skip patterns in this skip cluster because
they do not appear in the same clock cycle. The second skip cluster has a /K28.5/
control pattern in the MSByte of a clock cycle followed by two pairs of /K28.0/ skip
patterns in the next two cycles. The rate match FIFO deletes both pairs of /K28.0/
skip patterns (for a total of four skip patterns deleted) from the second skip cluster to
meet the three skip pattern deletion requirement.
Figure 1–83. Rate Match Deletion in Basic Double-Width Mode
First Skip Cluster
Two Pairs of Skip Patterns
Deleted
Second Skip Cluster
datain[19:10]
Dx.y
datain[9:0]
Dx.y
dataout[19:0]
Dx.y
dataout[9:0]
Dx.y
K28.0
K28.5
K28.0
K28.5
Dx.y
K28.0
Dx.y
K28.0
K28.5
Dx.y
K28.5
Dx.y
K28.0
K28.0
Dx.y
Dx.y
K28.0
K28.0
Dx.y
Dx.y
rx_rmfifodatadeleted
Figure 1–84 shows an example of rate match FIFO insertion in the case where three
skip patterns are required to be inserted. In this example, /K28.5/ is the control
pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a
/K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the MSByte of a
clock cycle followed by one /K28.0/ skip pattern in the LSByte of the next clock cycle.
The rate match FIFO inserts pairs of skip patterns in this skip cluster to meet the three
skip pattern insertion requirement.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation