HC4GX15 Datasheet, PDF (566/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–108
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
1 The logical reference index of CMU0 PLL within a transceiver block is
always the complement of the logical reference index of CMU1 PLL.
This logical reference index value is stored as logical tx pll, along with the other
transceiver channel settings in the .mif.
1 You can reuse the .mif generated for one CMU PLL to reconfigure the other
CMU PLL in the same or in other transceiver blocks.
ALTGX_RECONFIG MegaWizard Plug-In Manager Setup for CMU PLL Reconfiguration Mode
The settings available for CMU PLL Reconfiguration mode are listed below.
In addition to the first six settings listed in “ALTGX_RECONFIG MegaWizard Plug-In
Manager Setup for Channel and CMU PLL Reconfiguration Mode” on page 2–101,
you must set up the following input ports that are available for selection in the
Channel and TX PLL Reconfiguration screen:
The following input port is available for selection in the Error checks/Data rate
switch screen:
1. logical_tx_pll_sel and logical_tx_pll_sel_en—For more information
about these two ports, refer to “The logical_tx_pll_sel and logical_tx_pll_sel_en
Ports” on page 2–109.
2. rx_tx_duplex_sel[1:0]—This signal informs the dynamic reconfiguration
controller if the targeted transceiver channel configuration is Receiver only,
Transmitter only, or Receiver and Transmitter. The .mif also contains information
about the transceiver channel configuration. The ALTGX_RECONFIG
MegaWizard Plug-In Manager asserts the error signal if there is a mismatch
between the rx_tx_duplex_sel[1:0] signal and the .mif contents. For more
information, refer to “Dynamic Reconfiguration Controller Port List” on
page 2–11.
CMU PLL Reconfiguration Operation
1. Set the reconfig_mode_sel[2:0] signal to 3’b100 to activate this mode.
2. Set the logical_channel_address port to the logical channel address of the
transceiver channel connected to the CMU PLL.
3. Ensure that the busy signal is low.
4. Initiate a write transaction by asserting the write_all signal for one
reconfig_clk cycle to write the first 16-bit word of the .mif. Similarly, initiate a
write transaction to write all the words of the .mif. You can use the
reconfig_address_out_en port to determine when to initiate the next write
transaction.
The dynamic reconfiguration controller asserts the busy signal for every write
transaction initiated by you. The busy signal remains asserted until the complete
16-bit word has been written. The dynamic reconfiguration controller automatically
increments the values on the reconfig_address_out[5:0] port. During
reconfiguration, the dynamic reconfiguration controller powers down the CMU PLL
until new values are written. The dynamic reconfiguration controller asserts the
channel_reconfig_done signal to indicate that the CMU PLL reconfiguration is
complete.
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation