HC4GX15 Datasheet, PDF (200/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–4
Figure 2–2. Timing Closure ECO Flow Diagram
Chapter 2: HardCopy Design Center Implementation Process
HardCopy IV Back-End Design Flow
Placement
Merge New Cells
into Physical
Database
Clock Tree Synthesis
and High Fan-out
Net Buffering
Detailed Routing
ECO File
Preparation
Timing Closure
ECO Iterations
Static Timing Analysis
Timing
Violations
Timing Closed
Database
The back-end flow produces the final signoff timing for your HardCopy IV device.
The Quartus II software produces the timing report for HardCopy IV based on global
routing and does not factor in the exact physical parasitic of the routed nets. The
Quartus II software also does not factor in the crosstalk effect that neighboring nets
can have on interconnect capacitance.
Formal Verification of the Post-Layout Netlist
Besides the .gds2 file and parasitic files that are generated by the HardCopy Design
Center, the post-layout netlist is also generated for formal verification with Stratix IV
FPGAs. The HardCopy Design Center checks the functional equivalence between the
Stratix IV FPGA prototype and HardCopy IV device according to the Stratix IV .sof
file and HardCopy IV post-layout netlist.
HardCopy IV Device Handbook, Volume 2
© December 2008 Altera Corporation