HC4GX15 Datasheet, PDF (404/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–140
Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
PCI Express (PIPE) transmitter high-speed serial and low-speed parallel clock switch
occurs:
■ In PIPE ×1 mode, the CMU_PLL clock switch occurs in the local clock divider in
each transceiver channel.
■ In PIPE ×4 mode, the CMU_PLL clock switch occurs in the CMU0 clock divider in
the CMU0_Channel within the transceiver block.
■ In PIPE ×8 mode, the CMU_PLL clock switch occurs in the CMU0 clock divider in
the CMU0_Channel within the master transceiver block.
In PIPE ×1, ×4, and ×8 modes, the recovered clock switch happens in the receiver CDR
of each transceiver channel.
Table 1–37 lists the locations of the PIPE rateswitch controller and the PIPE clock
switch circuitry in PIPE ×1, ×2, ×4, and ×8 modes.
Table 1–37. PCI Express (PIPE) Rateswitch Controller and Clock Switch Circuitry
Channel
Bonding
Option
×1
×4
×8
Location of PCI Express (PIPE)
Rateswitch Controller Module
Location of PCI Express (PIPE) Clock Switch Circuitry
Transmitter High-Speed Serial and
Low-Speed Parallel Clock Switch
Circuitry
Recovered Clock Switch Circuitry
Individual channel PCS block Local clock divider in transmitter PMA CDR block in receiver PMA of each
of each channel
channel
CMU0 Channel
CMU0 clock divider in
CMU0_Channel
CDR block in receiver PMA of each
channel
CMU0 Channel of the
master transceiver block
CMU0 clock divider in
CMU0_Channel of the master
transceiver block
CDR block in receiver PMA of each
channel
Dynamic Switch Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rates in PCI
Express (PIPE) x1 Mode
Figure 1–113 shows the PCI Express (PIPE) rateswitch circuitry in PCI Express (PIPE)
×1 mode configured at Gen2 (5 Gbps) data rate.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation