HC4GX15 Datasheet, PDF (119/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
8–9
Receiver Data Realignment Circuit (Bit Slip)
Receiver Data Realignment Circuit (Bit Slip)
Skew in the transmitted data, along with skew added by the link, causes
channel-to-channel skew on the received serial data streams. If the DPA is enabled,
the received data is captured with different clock phases on each channel. This may
cause the received data to be misaligned from channel to channel. To compensate for
this channel-to-channel skew and establish the correct received word boundary at
each channel, each receiver channel has a dedicated data realignment circuit that
realigns the data by inserting bit latencies into the serial stream.
An optional RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each
receiver independently controlled from the internal logic. The data slips one bit for
every pulse on RX_CHANNEL_DATA_ALIGN. The following conditions are required
for the RX_CHANNEL_DATA_ALIGN signal:
■ The minimum pulse width is one period of the parallel clock in the logic array
■ The minimum low time between pulses is one period of the parallel clock
■ There is no maximum high or low time
■ Valid data is available two parallel clock cycles after the rising edge of
RX_CHANNEL_DATA_ALIGN
Figure 8–8 shows the receiver output (rx_out) after one bit slip pulse with the
serialization factor set to 4.
Figure 8–8. Data Realignment Timing
inclk
rx_in
rx_outclock
rx_channel_data_align
rx_out
32 10 32 10 32 10
3210
321x
xx21
0321
The data realignment circuit can have up to 11 bit-times of insertion before a rollover
occurs. The bit rollover point can be from 1 to 11 bit-times, independent of the
deserialization factor. An optional status port, rx_cda_max, is available to the FPGA
from each channel to indicate when the preset rollover point is reached.
Dynamic Phase Aligner (DPA)
The DPA block takes in high-speed serial data from the differential input buffer and
selects one of the eight phase clocks from the left or right PLL to sample the data. The
DPA chooses a phase closest to the phase of the serial data. The maximum phase
offset between the received data and the selected phase is 1/8 unit interval (UI),
which is the maximum quantization error of the DPA. The eight phases of the clock
are equally divided, giving a 45° resolution. Figure 8–9 shows the possible phase
relationships between the DPA clocks and the incoming serial data.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1