HC4GX15 Datasheet, PDF (105/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 7: External Memory Interfaces in HardCopy IV Devices
7–39
HardCopy IV External Memory Interface Features
Figure 7–27. HardCopy IV IOE Input Registers (Note 1)
DQ
DQS (3)
CQn (4)
Double Data Rate Input Registers
DQ
DFF
Input Reg A _I
D
Q ^neg_reg_out D
Q
DFF
Input Reg BI
DFF
Input Reg CI
0
1
Resynchronization
Clock
(resync_clk_2x)
(5)
Alignment & Synchronization Registers
DQ
DFF
D
Q
DFF
D
Q
DFF
D
Q
DFF
DQ
DFF
(2)
DQ
DFF
Half Data Rate Registers
DQ
DFF
DQ
To Core
(rdata1)
D
Q ⁽⁷⁾
DFF
DFF
DQ
DFF
DQ
DFF
To Core
(rdata3)
(7)
DQ
DFF
0 To Core (rdata0)
1
(7)
dataoutbypass
(8)
0 To Core (rdata2)
1
(7)
I/O Clock
Divider (6)
Half-Rate Resynchronization Clock (resync_clk_1x)
to core (7)
Notes to Figure 7–27:
(1) You can bypass each register block in this path.
(2) This is the 0-phase resynchronization clock from the read-leveling delay chain.
(3) The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line.
(4) This input clock comes from the CQn logic block.
(5) This resynchronization clock can come either from the PLL or from the read-leveling delay chain.
(6) The I/O clock divider resides adjacent to the DQS logic block. In addition to the PLL and read levelled resync clock, the I/O clock divider can also
be fed by the DQS bus or CQn bus.
(7) The half-rate data and clock signals feed into a FIFO in the core.
(8) You can change the dataoutbypass signal dynamically after the device enters user mode.
There are three registers in the DDR input registers block. Two registers capture data
on the positive and negative edges of the clock, while the third register aligns the
captured data. You can choose to have the same clock for the positive edge and
negative edge registers, or two different clocks (DQS for positive-edge register, and
CQn for negative-edge register). The third register that aligns the captured data uses
the same clock as the positive-edge register.
The resynchronization registers consist of up to three levels of registers to
resynchronize the data to the system clock domain. These registers are clocked by the
resynchronization clock that is either generated by the PLL or the read-leveling delay
chain. The outputs of the resynchronization registers can go straight to the core or to
the HDR blocks, which are clocked by the divided-down resynchronization clock.
For more information about the read-leveling delay chain, refer to “Leveling
Circuitry” on page 7–36.
Figure 7–28 shows the registers available in the HardCopy IV output and
output-enable paths. The path is divided into the HDR block, resynchronization
registers, and output/output-enable registers. The device can bypass each block of the
output and output-enable path.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1