HC4GX15 Datasheet, PDF (193/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV Design Flow Using the Quartus II Software
1–25
Engineering Change Order (ECO)
f For a summary of suggested implementation changes, refer to the Quartus II Support
for HardCopy Series Devices chapter in volume 1 of the Quartus II Handbook.
PLL settings are another example of implementing changes differently on the Stratix
FPGA and the HardCopy ASIC revisions. Sometimes PLL-generated clocks must be
modified to provide a higher-frequency clock in HardCopy devices to improve the
performance of the HardCopy device without changing the performance of the Stratix
FPGA. You must handle the modification correctly so that the HardCopy Companion
Revision Comparison utility does not generate critical errors.
To set different PLL settings for the Stratix FPGA and HardCopy revisions, you must
have different PLL source files. Each PLL must have the same module name, so that
the same PLL in both revisions is not treated differently during the HardCopy
Revision Comparison stage. You must have two PLL files with different names that
reference the same module.
When starting HardCopy development with the FPGA first flow to override the file
naming convention so that the same PLL module can be referenced by two different
PLL files, complete the following steps:
1. Specify the PLL source file in the QSF file in the Stratix FPGA revision.
For example, set_global_assignment -name
MIGRATION_DIFFERENT_SOURCE_FILE pll_fgpa.v
1 Note that when there are multiple PLL source files, you must use multiple
assignments to specify the PLL source files.
2. Compile the Stratix FPGA revision in the Quartus II software.
3. After creating the HardCopy revision, modify the PLL source file manually or
with the MegaWizard Plug-In Manager in order to improve the performance in
the HardCopy revision.
1 When the MegaWizard Plug-In Manager updates the new source file, it
modifies the top-level name of the module or entity in the source file to
match the name of the source file. Therefore, you must rename the module
or entity after you have updated the file with the MegaWizard Plug-In
Manager so that your top-level design instantiates the PLL with the newly
modified PLL design file.
4. After updating the PLL source file in the HardCopy revision, verify that the QSF
source file setting contains the newly modified PLL source file. For example,
set_global_assignment -name VERILOG_FILE pll_hc.v
5. Compile the HardCopy revision in the Quartus II software.
After compilation is completed, run the HardCopy companion Revision Comparison
utility to observe and track the changes made to the PLLs and design settings. These
changes are captured as critical warnings in the revision comparison report and must
be reviewed by the HardCopy Design Center before the design is accepted for
mapping.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 2