HC4GX15 Datasheet, PDF (405/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–141
Figure 1–113. Dynamic Switch Signaling in PIPE ×1 Mode
Core Fabric
PIPE
Interface
Transceiver PCS
Receiver
Phase
Comp
FIFO
reset_int
Transmitter
Phase
Comp
FIFO
reset_int
rx_locktorefclk
rx_locktodata
signal detect
rx_freqlocked
rx_datain
LTR/LTD
Controller
Phase
Detector
(PD)
/1, /2,
rx_cruclk _/4
/2
pcie_gen2switch
Phase
Frequency
Detector
(PFD)
Transceiver Channel
Clock and Data Recovery (CDR) Unit
1
0
/2
Charge
Pump +
Loop
Filter
pcie_gen2switch
VCO /L
/M
Serial Recovered Clock
Parallel Recovered Clock
pipephydonestatus
rateswitch
PCI
Express
Rate
Switch
Controller
pcie_gen2switch
pcie_gen2switch_done
CMU0_PLL
Output Clock
CMU1_PLL
Output Clock
/1, /2, /4
PCI
Express
Clock
Switch
Circuitry
Local Clock Divider
4, /5, /8, /10
High-Speed Serial Clock
Low-Speed Parallel Clock
PCI Express Clock Switch Circuitry
In PIPE ×1 mode configured at Gen2 (5 Gbps) data rate, when the PIPE rateswitch
controller sees a transition on the rateswitch signal, it sends control signal
pcie_gen2switch to the PIPE clock switch circuitry in the local clock divider block
and the receiver CDR to switch to the instructed signaling rate. A low-to-high
transition on the rateswitch signal initiates a Gen1 (2.5 Gbps) to Gen2 (5 Gbps)
signaling rateswitch. A high-to-low transition on the rateswitch signal initiates a
Gen2 (5 Gbps) to Gen1 (2.5 Gbps) signaling rateswitch.
Table 1–38 shows transceiver clock frequencies when switching between 2.5 Gbps and
5 Gbps signaling rates.
Table 1–38. Transceiver Clock Frequencies Signaling Rates in PCI Express (PIPE) ×1 Mode
Transceiver Clocks
High-Speed Serial Clock
Low-Speed Parallel Clock
Serial Recovered Clock
Parallel Recovered Clock
Core Fabric-Transceiver Interface Clock
Gen1 (2.5 Gbps) to Gen2 (5 Gbps)
Switch
(Low-to-High Transition on the
rateswitch Signal)
1.25 GHz to 2.5 GHz
250 MHz to 500 MHz
1.25 GHz to 2.5 GHz
250 MHz to 500 MHz
125 MHz to 250 MHz
Gen2 (5 Gbps) to Gen1 (2.5 Gbps)
Switch
(High-to-Low Transition on the
rateswitch Signal)
2.5 GHz to 1.25 GHz
500 MHz to 250 MHz
2.5 GHz to 1.25 GHz
500 MHz to 250 MHz
250 MHz to 125 MHz
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3