HC4GX15 Datasheet, PDF (279/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–15
Transceiver Port List
Table 1–2. HardCopy IV GX ALTGX Megafunction Ports (Part 8 of 14)
Port Name
rx_phase_comp_fifo_error
Input/Output
Description
Output
Receiver phase compensation FIFO full or
empty indicator. A high level indicates that the
receiver phase compensation FIFO is either full
or empty.
Receiver Physical Media Attachment (PMA)
rx_datain
Input
rx_cruclk
Input
rx_pll_locked
Output
rx_freqlocked
Output
rx_locktodata
rx_locktorefclk
Input
Input
Receiver serial data input port.
Input reference clock for the receiver clock and
data recovery.
Receiver CDR lock-to-reference (LTR) indicator.
A high level indicates that the receiver CDR is
locked to the input reference clock. A low level
indicates that the receiver CDR is not locked to
the input reference clock.
Asynchronous signal.
Receiver CDR lock mode indicator. A high level
indicates that the receiver CDR is in
lock-to-data (LTD) mode. A low level indicates
that the receiver CDR is in lock-to-reference
mode.
Asynchronous signal.
Receiver CDR lock-to-data mode control signal.
When asserted high, the receiver CDR is forced
to lock-to-data mode. When de-asserted low,
the receiver CDR lock mode depends on the
rx_locktorefclk signal level.
Receiver CDR lock-to-reference mode control
signal.
The rx_locktorefclk signal along with
the rx_locktodata signal controls whether
the receiver CDR is in lock-to-reference or
lock-to-data mode, as follows:
rx_locktodata/
rx_locktorefclk
0/0–receiver CDR is in automatic mode
0/1–receiver CDR is in LTR mode
1/x–receiver CDR is in LTD mode
Asynchronous signal.
Scope
Channel
Channel
Channel
Channel
Channel
Channel
Channel
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3