HC4GX15 Datasheet, PDF (309/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–45
Transmitter Channel Datapath
The following is an example of an invalid control word encoded into a valid Dx.y
code. With an encoding of an invalid code K24.1 (tx_datain = 8'h38 + tx_ctrl
= 1'b1), depending on the current running disparity, the K24.1 can be encoded to be
10'b0110001100 (0 × 18C), which is equivalent to a D24.6+ (8'hD8 from the RD+
column). An 8B/10B decoder can decode this and not assert a code error flag.
1 Altera does not recommend sending invalid control words to the 8B/10B encoder.
Reset Condition
The tx_digitalreset signal resets the 8B/10B encoder. During reset, the running
disparity and data registers are cleared. Also, the 8B/10B encoder outputs a K28.5
pattern with proper disparity continuously until tx_digitalreset goes low. The
inputs from the tx_datain and tx_ctrlenable ports are ignored during the reset
state. After reset, the 8B/10B encoder starts the LSByte with a negative disparity (RD-)
and the MSByte with a positive disparity (RD+) and transmits six K28.5 code groups
(three on the LSByte and three on the MSByte encoder) for synchronizing before it
starts encoding and transmitting data.
1 If the tx_digitalreset signal is asserted, the downstream 8B/10B decoder
receiving the data might get synchronization or disparity errors.
Figure 1–32 shows the reset behavior of the 8B/10B encoder. When in reset
(tx_digitalreset is high), a K28.5- is sent continuously until tx_digitalreset
is low. Due to pipelining of the TX channel, there will be some “don’t cares” (10'hxxx)
until the first K28.5 is sent (Figure 1–32 shows six “don’t cares”, but the number of
“don’t cares” can vary). Both the LSByte and MSByte transmit three K28.5s before the
data at the tx_datain port is encoded and sent out.
Figure 1–32. Transmitted Output Data when tx_digitalreset is Asserted
clock
tx_digitalreset
dataout[19:10]
k28.5- k28.5- k28.5-
xxx
xxx
xxx
k28.5+ k28.5+ k28.5+ Dx.y+
dataout[9:0]
k28.5+ k28.5+ k28.5+
xxx
xxx
xxx
k28.5- k28.5- k28.5- Dx.y-
Controlling Running Disparity
After power on or reset, the 8B/10B encoder has a negative disparity and chooses the
10-bit code from the RD- column (refer to the 8B/10B encoder specification for the
RD+ and RD- column values). The ALTGX MegaWizard Plug-In Manager provides
the tx_forcedisp and tx_dispval ports to control the running disparity of the
output from the 8B/10B encoder. These ports are available only in Basic single-width
and Basic double-width modes.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3