HC4GX15 Datasheet, PDF (322/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
Figure 1–45 shows the transmitter local clock divider block.
Figure 1–45. Transmitter Local Clock Divider Block
CMU0 PLL High-Speed Clock
CMU1 PLL High-Speed Clock
÷n
÷1, 2, or 4
÷ 4, 5, 8, or 10
High-Speed
Serial Clock
Low-Speed
Parallel Clock
Receiver Channel Datapath
This section describes HardCopy IV GX receiver channel datapath architecture. The
sub-blocks in the receiver datapath are described in order from the serial receiver
input buffer to the receiver phase compensation FIFO buffer at the core
fabric-transceiver interface.
Figure 1–46 shows the receiver channel datapath in HardCopy IV GX devices.
Figure 1–46. Receiver Channel Datapath
Core
Fabric
PCI Express
hardIP
PIPE
Interface
RX Phase
Compensation
FIFO
Byte
Ordering
Byte
De-
Serializer
8B/10B
Decoder
Rate
Match
FIFO
Receiver Channel PCS
Deskew
FIFO
Word
Aligner
Receiver Channel PMA
De-
Serializer
CDR
Serial Input Data
rx_datain
Input Reference
Clock
The receiver channel PMA datapath consists of the following blocks:
■ Receiver input buffer
■ Clock and data recovery (CDR) unit
■ Deserializer
The receiver channel PCS datapath consists of the following blocks:
■ Word aligner
■ Deskew FIFO
■ Rate match (clock rate compensation) FIFO
■ 8B/10B decoder
■ Byte deserializer
■ Byte ordering
■ Receiver phase compensation FIFO
■ PCI Express (PIPE) interface
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation