HC4GX15 Datasheet, PDF (270/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–6
Chapter 1: HardCopy IV GX Transceiver Architecture
Transceiver Block Architecture
Figure 1–5. HardCopy IV GX Devices with Thirty-Six Transceiver Channels
HC4GX35FF1517N
Transceiver Block GXBL2
Channel 3
Channel 2
CMU Channel 1
CMU Channel 0
Channel 1
Channel 0
Transceiver Block GXBR2
Channel 3
Channel 2
CMU Channel 1
CMU Channel 0
Channel 1
Channel 0
Transceiver Block GXBL1
Channel 3
Channel 2
CMU Channel 1
CMU Channel 0
Channel 1
Channel 0
Transceiver Block GXBL0
Channel 3
Channel 2
CMU Channel 1
CMU Channel 0
Channel 1
Channel 0
Transceiver Block GXBR1
Channel 3
Channel 2
CMU Channel 1
CMU Channel 0
Channel 1
Channel 0
Transceiver Block GXBR0
Channel 3
Channel 2
CMU Channel 1
CMU Channel 0
Channel 1
Channel 0
Transceiver Block Architecture
Each transceiver block has the following components:
■ Two clock multiplier unit (CMU) channels—the CMU0 and CMU1 channels—that
provide the high-speed serial and low-speed parallel clock to the transceiver
channels
■ Four full-duplex (transmitter and receiver) transceiver channels that support serial
data rates from 600 Mbps to 6.5 Gbps
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation