HC4GX15 Datasheet, PDF (590/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–132
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Design Examples: Dynamic Reconfiguration Controller
Table 2–37. Differences between GIGE and SONET/SDH OC48 (Part 2 of 2)
Number
7
8
Functional Block
Allowed input reference
clock frequencies
GIGE
62.5 MHz
125 MHz
PCS-PMA interface width
10
(because data is 8B/10B
encoded)
SONET/SDH OC48
77.76 MHz
155.52 MHz
311.04 MHz
622.08 MHz
8
These differences determine the selection of parameters in the ALTGX MegaWizard
Plug-In Manager and the required core array to dynamically reconfigure a transceiver
channel between these two configurations. Figure 2–58 shows the required functional
blocks to perform channel reconfiguration.
Figure 2–58. Dynamically Reconfiguring between GIGE and SONET/SDH OC48 Configurations
User Logic in the Core Fabric
Transceiver Interfaces
User logic for GIGE and
SONET / SDH datapath
Reset Control Logic
RAM Initializer
(ALTMEM_INIT)
containing the
GIGE .mif
RAM
RAM Initializer
(ALTMEM_INIT)
containing the
SONET/SDH .mif
RAM
User Control logic to
control the
ALTGX_RECONFIG
interface
Dynamic
Reconfiguration
Controller
(ALTGX_RECONFIG)
ALTGX
Interface
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation