HC4GX15 Datasheet, PDF (388/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–124
Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
Figure 1–104. Transceiver Datapath When in Deterministic Latency Mode
PCI
Express
hardIP
PIPE
Interface
TX Phase
Compensation
FIFO
Transmitter Channel PCS
Byte
Serializer
8B/10B
Encoder
Transmitter Channel PMA
Serializer
Bit slip
Core
Fabric
PCI
Express
hardIP
PIPE
Interface
RX Phase
Compensation
FIFO
Receiver Channel PCS
Byte
De-
Serializer
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Receiver Channel PMA
De-
Serialzier
CDR
To implement deterministic latency mode under the Basic functional mode, the
transmitter must be placed in bit-slip mode, the receiver’s phase compensation FIFO
must be placed in register mode and a port on the receiver,
rx_bitslipboundaryselectout[4:0] should be used. For example, for a full
duplex (with both receiver and transmitter channels) link, you must select Enable the
RX phase comp FIFO in register mode in the ALTGX MegaWizard Plug-In Manager.
When this option is selected, the transmitter is placed in bit-slipping mode and the
tx_bitslipboundaryselect[4:0] port is automatically available. Similarly, the
rx_bitslipboundaryselectout[4:0] output port is automatically available.
Rx Bit Slipping
The number of bits slipped in the receiver’s word aligner is given out on the
rx_bitslipboundaryselectout[4:0] output port. The information on this
output depends on your deserializer block width.
In single-width mode with 8/10-bit channel width, the number of bits slipped in the
receiver path is given out sequentially on this output. For example, if zero bits are
slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of
0(00000); if two bits are slipped, the output on
rx_bitslipboundaryselectout[4:0] shows a value of 2 (00010).
In double-width mode with 16/20-bit channel width, the output is 19 minus the
number of bits slipped. For example, if 0 bits are slipped, the output on
rx_bitslipboundaryselectout[4:0] shows a value of 19 (10011); if two bits are
slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of
17 (10001).
The information on the rx_bitslipboundaryselectout[4:0] output port helps
in calculating the latency through the receiver datapath. You can use the information
on rx_bitslipboundaryselectout[4:0] to set up the
tx_bitslipboundaryselect[4:0] appropriately to cancel out the latency
uncertainty.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation