HC4GX15 Datasheet, PDF (454/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–190
Chapter 1: HardCopy IV GX Transceiver Architecture
Loopback Modes
The status signals rx_bistdone and rx_bisterr indicate the status of the verifier.
The rx_bistdone port is asserted and stays high when the verifier either receives
one full cycle of incremental pattern or it detects an error in the receiver data. The
rx_bisterr signal is asserted and stays high when the verifier detects an error. You
can reset the incremental pattern generator and verifier by asserting the
tx_digitalreset and rx_digitalreset signals, respectively.
Reverse Serial Loopback
Reverse serial loopback is available as a subprotocol under Basic functional mode. In
reverse serial loopback mode, the data is received through the rx_datain port,
retimed through the receiver CDR and sent out to the tx_dataout port. The received
data is also available to the core logic. Figure 1–158 shows the transceiver channel
datapath for reverse serial loopback mode. The active block of the transmitter channel
is only the transmitter buffer. You can change the output differential voltage on the
transmitter buffer through the ALTGX MegaWizard Plug-In Manager. The
pre-emphasis settings for the transmitter buffer cannot be changed in this
configuration. Reverse serial loopback is often implemented when using a bit error
rate tester (BERT) on the upstream transmitter.
Figure 1–158. Reverse Serial Loopback Datapath (Grayed-Out Blocks are Not Active in this Mode)
TX Phase
Compen-
sation
FIFO
Byte
Serialzier
Transmitter Channel PCS
8B/10B
Encoder
Transmitter Channel PMA
Serializer
Core
Fabric
Receiver Channel PCS
Receiver Channel PMA
Reverse
Serial
Loopback
RX Phase
Compen-
sation
FIFO
Byte
Ordering
Byte
De-
Serializer
8B/10B
Decoder
Word
Aligner
De-
Serializer
Receiver
CDR
Reverse Serial Pre-CDR Loopback
The reverse serial pre-CDR loopback is available as a subprotocol under Basic
functional mode. In reverse serial pre-CDR loopback, the data received through the
rx_datain port is looped back to the tx_dataout port before the receiver CDR. The
received data is also available to the core logic. Figure 1–159 shows the transceiver
channel datapath for reverse serial pre-CDR loopback mode. The active block of the
transmitter channel is only the transmitter buffer. You can change the output
differential voltage and the pre-emphasis first post-tap values on the transmitter
buffer through the ALTGX MegaWizard Plug-In Manager or through the dynamic
reconfiguration controller. The pre-tap and second post-tap values cannot be changed
in this loop back configuration.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation