HC4GX15 Datasheet, PDF (284/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–20
Chapter 1: HardCopy IV GX Transceiver Architecture
Transceiver Port List
Table 1–2. HardCopy IV GX ALTGX Megafunction Ports (Part 13 of 14)
Port Name
pipe8b10binvpolarity
tx_detectrxloopback
pipestatus
pipephydonestatus
Input/Output
Description
Input
PCI Express (PIPE) polarity inversion control.
Functionally equivalent to the rxpolarity
signal defined in the PIPE specification revision
2.0. This feature is available only in PIPE mode.
When asserted high, the polarity of every bit of
the 10-bit input data to the 8B/10B decoder gets
inverted.
Input
Receiver detect or PCI Express (PIPE) loopback
control. This feature is functionally equivalent
to the txdetectrx/loopback signal
defined in the PIPE specification revision 2.0.
When asserted high in the P1 power state with
the tx_forceelecidle signal asserted,
the transmitter buffer begins the receiver
detection operation. After the receiver detect
completion is indicated on the
pipephydonestatus port, this signal must
be de-asserted.
When asserted high in the P0 power state with
the tx_forceelecidle signal de-asserted,
the transceiver datapath gets dynamically
configured to support parallel loopback as
described in “PCI Express (PIPE) Reverse
Parallel Loopback” on page 1–191.
Output
PIPE receiver status port. This feature is
functionally equivalent to the
rxstatus[2:0] signal defined in the PIPE
specification revision 2.0. The width of this
signal is 3-bits per channel. The encoding of
receiver status on the pipestatus port is as
follows:
■ 000–Received data OK
■ 001–1 skip added
■ 010–1 skip removed
■ 011–Receiver detected
■ 100–8B/10B decoder error
■ 101–Elastic buffer overflow
■ 110–Elastic buffer underflow
Output
■ 111–Received disparity error
PHY function completion indicator. This feature
is functionally equivalent to the phystatus
signal defined in the PIPE specification revision
2.0. Assert this signal high for one parallel clock
cycle to communicate completion of several
PHY functions, such as power state transition,
receiver detection, and signaling rate change
between Gen1 (2.5 Gbps) and Gen2 (5 Gbps).
Scope
Channel
Channel
Channel
Channel
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation