HC4GX15 Datasheet, PDF (51/668 Pages) Altera Corporation – HardCopy IV Device Handbook

6. HardCopy IV Device I/O Features
HIV51006-2.1
This chapter documents I/O standards, features, termination schemes, and
performance supported in HardCopy^® IV devices. All HardCopy IV devices have
configurable high-performance I/O drivers and receivers supporting a wide range of
industry standard interfaces. Both the top/bottom (column) and left/right (row) I/O
banks of HardCopy IV devices support the same I/O standards with different
performance specifications.
This chapter includes the following sections:
■ “Differences Between HardCopy IV ASICs and Stratix IV FPGAs” on page 6–2
■ “I/O Standards and Voltage Levels” on page 6–3
■ “HardCopy IV I/O” on page 6–5
■ “HardCopy IV I/O Banks” on page 6–8
■ “HardCopy IV I/O Structure” on page 6–10
■ “MultiVolt I/O Interface” on page 6–10
■ “3.3- and 3.0-V I/O Interface” on page 6–11
■ “External Memory Interfaces” on page 6–12
■ “High-Speed Differential I/O with DPA Support” on page 6–12
■ “On-Chip Termination Support and I/O Termination Schemes” on page 6–12
■ “OCT Calibration Block Location” on page 6–13
■ “Design Considerations” on page 6–13
Numerous I/O features assist in high-speed data transfer into and out of the
HardCopy device.
HardCopy IV GX I/O Support:
■ Up to 32 full-duplex clock data recovery (CDR)-based transceivers supporting
data rates between 600 Mbps and 6.5 Gbps
■ Dedicated circuitry to support physical layer functionality for popular serial
protocols, such as PCI Express (PIPE) Gen1 and Gen2, Gigabit Ethernet, Serial
RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre
Channel, SFI-5, and Interlaken
■ Complete PCI Express (PIPE) protocol solution with embedded PCI Express hard
IP blocks that implement PHY-MAC layer, data-link layer, and transaction layer
functionality
Supported I/O standards:
■ Single-ended, non-voltage-referenced or voltage-referenced I/O standards;
low-voltage differential signaling (LVDS); reduced swing differential signal
(RSDS); mini-LVDS; high-speed transceiver logic (HSTL); and stub series
terminated logic (SSTL)
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1