HC4GX15 Datasheet, PDF (199/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy Design Center Implementation Process
2–3
HardCopy IV Back-End Design Flow
Parasitic Extraction and Timing Analysis
After the HardCopy Design Center places and routes your design, a .gds2 design file
is generated. Parasitic extraction uses the physical layout of the design stored in the
database to extract the resistance and capacitance values for all signal nets in the
design. The HardCopy Design Center uses these parasitic values to calculate the path
delays through the design for static timing analysis and crosstalk analysis.
Back-End Timing Closure
The Quartus II software provides a pre-layout estimation of your HardCopy IV
design performance. The Altera HardCopy Design Center then uses industry leading
EDA software to complete the back-end layout and extract the final timing results
prior to tape-out. Altera performs rigorous timing analysis on the HardCopy IV
design during its back-end implementation, ensuring that it meets the required
timing constraints. After generating the customized metal interconnect for the
HardCopy IV device, Altera checks the design timing with a static timing analysis
tool. The static timing analysis tool may report timing violations, which are reviewed
with the customer.
The critical timing paths of the HardCopy IV device may be different from the
corresponding paths in the Stratix IV FPGA revision; these differences can exist for
several reasons. While maintaining the same set of features as the corresponding
Stratix IV FPGA, HardCopy IV devices have a highly optimized die size to make them
as small as possible. Because of the customized interconnect structure that makes this
optimization possible, the delay through each signal path is different from the
original Stratix IV FPGA design. Therefore, it is important to constrain the Stratix IV
FPGA and HardCopy IV devices to the exact, system-level timing requirements that
need to be achieved. Timing violations seen in the Quartus II project or in the
HardCopy Design Center back-end process must be fixed or waived prior to the
design tape-out.
Timing ECOs
In an ASIC design, small incremental changes to a design database are termed ECOs.
In the HardCopy IV design flow, timing closure ECOs are performed by Altera’s
HardCopy Design Center after the initial post-layout timing data is available.
The Altera HardCopy Design Center runs static timing analysis on the design. This
analysis may show that the place and route tool was not able to close timing
automatically on some paths. The HardCopy Design Center engineer will determine
the best way to fix the timing on these paths (for example, by adding delay cells to fix
a hold time violation). This list of changes is fed back into the place and route tool
which subsequently implements the changes. The impact to the place and route
database is minimized by maintaining all of the pre-existing placement and routing,
and only changing the paths that need improvement.
The parasitic resistances and capacitances of the customized interconnect are
extracted, and are used in conjunction with the static timing analysis tool to re-check
the timing of the design. Detected crosstalk violations on signals are fixed by adding
additional buffering to increase the setup or hold margin on victim signals. In-line
buffering and small buffer tree insertion is done for signals with high fanout, high
transition times, or high capacitive loading. Figure 2–2 shows this flow in more detail.
© December 2008 Altera Corporation
HardCopy IV Device Handbook, Volume 2