HC4GX15 Datasheet, PDF (182/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV Design Flow Using the Quartus II Software
Quartus II Settings for HardCopy IV Devices
1 Beginning with the Quartus II v9.0 software, the Physical Synthesis Optimizations
settings changed. If a HardCopy IV device is set as a companion device, the Physical
Synthesis Optimization setting in the Stratix IV FPGA or HardCopy IV ASIC
revision supports the Perform physical synthesis for combination logic and Perform
register retiming options. In addition, the effort level of physical synthesis
optimization is set to Fast by default.
Timing Settings
For HardCopy IV device development, you must use the TimeQuest Timing
Analyzer. In the Quartus II software, TimeQuest Timing Analyzer is the default
timing analyzer for Stratix IV and HardCopy IV designs. The TimeQuest Timing
Analyzer guides the Quartus II Fitter and analyzes timing results during each
Stratix IV and HardCopy IV design compilation.
For information about how to set the Quartus II Fitter to use timing-driven
compilation, refer to “Quartus II Fitter Settings” on page 1–19.
Timing Constraints for the TimeQuest Timing Analyzer
The TimeQuest Timing Analyzer is a powerful ASIC-style timing analysis tool that
validates timing in your design using industry-standard constraint, analysis, and
reporting methodology. You can use the TimeQuest analyzer ’s GUI or command-line
interface to constrain, analyze, and report results for all timing paths in your design.
Before running the TimeQuest analyzer, you must specify initial timing constraints
that describe the clock characteristics, timing exceptions, signal transition arrival, and
required times. You can specify timing constraints in the Synopsys Design
Constraints File (.sdc) format using the TimeQuest analyzer GUI or the command-line
interface. The Quartus II Fitter optimizes the placement of logic to meet your
constraints.
The TimeQuest analyzer analyzes the timing paths in the design, calculates the
propagation delay along each path, checks for timing constraint violations, and
reports timing results as slack in the Report and Console panels. If the TimeQuest
analyzer reports any timing violations, you can customize the reporting to view
precise timing information about the specific paths, and then constrain those paths to
correct the violations. When your design is free of timing violations, you can be
confident that the logic will operate as intended in the target device.
The TimeQuest analyzer is a complete static timing analysis tool that you can use as a
sign-off tool for the Stratix IV design. For the HardCopy IV design, the Altera
HardCopy Design Center uses the PrimeTime timing analyzer as the sign-off tool for
back-end implementation.
f For more information about how to create .sdc format timing constraints, refer to the
Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook.
HardCopy IV Device Handbook, Volume 2
© January 2010 Altera Corporation