HC4GX15 Datasheet, PDF (359/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–95
Receiver Channel Datapath
Figure 1–71 shows an example of rate match deletion in the case where two /K28.0/
SKP symbols are required to be deleted. Only one /K28.0/ SKP symbol is deleted per
SKP ordered set received.
Figure 1–71. Rate Match Deletion in PCI Express (PIPE) Mode
SKIP Symbol Deleted
First Skip Ordered Set
Second Skip Ordered Set
datain
K28.5
K28.0
Dx.y
K28.5
K28.0
K28.0
K28.0
dataout
K28.5
Dx.y
K28.5
K28.0
K28.0
K28.0
pipestatus[2:0]
3'b010
xxx
3'b010
xxx
xxx
xxx
Figure 1–72 shows an example of rate match insertion in the case where two SKP
symbols are required to be inserted. Only one /K28.0/ SKP symbol is inserted per
SKP ordered set received.
Figure 1–72. Rate Match Insertion in PCI Express (PIPE) Mode
First Skip Ordered Set
SKIP Symbol Inserted
Second Skip Ordered Set
datain
K28.5
K28.0
Dx.y
K28.5
K28.0
K28.0
K28.0
K28.0
dataout
K28.5
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
pipestatus[2:0]
3'b001
xxx
xxx
xxx
3'b001
xxx
xxx
xxx
xxx
xxx
The rate match FIFO full and empty conditions are communicated to the core fabric
on the pipestatus[2:0] port from each channel.
The rate match FIFO in PIPE mode automatically deletes the data byte that causes the
FIFO to go full and drives pipestatus[2:0] = 3'b101 synchronous to the
subsequent data byte.
Figure 1–73 shows the rate match FIFO full condition in PIPE mode. The rate match
FIFO becomes full after receiving data byte D4.
Figure 1–73. Rate Match FIFO Full Condition in PCI Express (PIPE) Mode
datain
D1
D2
D3
D4
D5
D6
D7
D8
dataout
D1
D2
D3
D4
D6
D7
D8
xx
xx
xx
pipestatus[2:0]
xxx
xxx
xxx
xxx
3'b101
xxx
xxx
xxx
The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that
causes the FIFO to go empty and drives PCI Express (PIPE)status[2:0] =
3’b110 flag synchronous to the inserted /K30.7/ (9'h1FE).
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3