HC4GX15 Datasheet, PDF (466/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–8
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic
Figure 2–3. Block Diagram of the Dynamic Reconfiguration Controller
reconfig_clk
read
write_all
reconfig_fromgxb[]
Dynamic Reconfiguration Controller
PMA controls
reconfig
logic
PMA control ports (1)
rate_switch_ctrl[1:0] (TX only)
Data Rate
Switch
control logic
reset_reconfig_address
reconfig_data[15:0]
logical_tx_pll_sel
logical_tx_pll_sel_en
logical_channel_address[]
rx_tx_duplex_sel[1:0]
CMU PLL
reconfig
control logic
Channel
and CMU PLL
reconfig
control logic
Channel
reconfig with
TX PLL
select control
logic
Offset
Cancellation
control logic
Address
Translation
addr
Parallel to
Serial
Converter
data
reconfig_togxb[3:0]
data valid
busy
error
rate_switch_out[1:0] (TX only)
reconfig_address_out[5:0]
reconfig_address_en
channel_reconfig_done
reconfig_mode_sel[2:0]
Note to Figure 2–3:
(1) The PMA control ports consist of the V_OD controls, pre-emphasis controls, DC gain controls, and manual equalization controls. For a detailed
description of all the inputs and outputs of the ALTGX_RECONFIG instance, refer to “Dynamic Reconfiguration Controller Port List” on page 2–11.
The dynamic reconfiguration controller has the following control logic modules:
■ PMA controls reconfiguration control logic
■ Offset cancellation control logic for receiver channels
■ Data rate division control logic to the TX local divider
■ Channel reconfiguration with TX PLL select/reconfig control logic
■ CMU PLL reconfiguration control logic
■ Channel and CMU PLL reconfiguration control logic
■ Channel reconfiguration with TX PLL select control logic
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation