HC4GX15 Datasheet, PDF (477/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
2–19
Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration
Table 2–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 9 of 9)
Port Name
Input/
Output
Description
rate_switch_ctrl[1:0]
Input
This signal is available when you select Data Rate Division in TX
mode. Based on the value you set here, the divide-by setting of the
local divider in the transmitter channel gets modified. The legal
values for this port are:
2’b00 – Divide by 1
2’b01 – Divide by 2
2’b10 – Divide by 4
2’b11 – Not supported
For more information, refer to “Data Rate Division in TX Mode” on
page 2–63.
rate_switch_out[1:0]
Input
This signal is available when you select Data Rate Division in TX
mode. You can read the existing local divider settings of a
transmitter channel at this port. The decoding for this signal is
listed below:
2’b00 – Division of 1
2’b01 – Division of 2
2’b10 – Division of 4
2’b11– Not supported
For more information, refer to “Data Rate Division in TX: Operation”
on page 2–66.
logical_tx_pll_sel
Input
At this port you specify the identity of the TX PLL you want to
reconfigure. You can also specify the identity of the TX PLL that you
want the transceiver channel to listen to. When you enable this
signal, the value set at this signal overwrites the
logical_tx_pll value contained in the .mif. The value at this
port needs to be held at a constant logic level until reconfiguration
is done.
logical_tx_pll_sel_en
Input
If you want to use the logical_tx_pll_sel port only under
some conditions and use the logical_tx_pll value contained
in the .mif otherwise, enable this optional
logical_tx_pll_sel_en port. Only when
logical_tx_pll_sel_en is enabled and set to 1 does the
dynamic reconfiguration controller use logical_tx_pll_sel
to identify the TX PLL. The value at this port needs to be held at a
constant logic level until reconfiguration is done.
channel_reconfig_done
Output
This signal goes high for one reconfig_clk clock cycle to
indicate that the dynamic reconfiguration controller has finished
writing all the words of the .mif. This signal is applicable only in
Channel and CMU PLL reconfiguration and Channel reconfiguration
with TX PLL select modes.
Notes to Table 2–2:
(1) Not all combinations of the input bits are legal values.
(2) In PCI Express (PIPE) mode, this input needs to be tied to 001 to be PCI E-compliant.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3