HC4GX15 Datasheet, PDF (116/668 Pages) Altera Corporation – HardCopy IV Device Handbook

8–6
Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
Differential Transmitter
Differential Transmitter
The HardCopy IV transmitter has dedicated circuitry to provide support for LVDS
signaling. The dedicated circuitry consists of a differential buffer, a serializer, and a
shared analog PLL (left or right PLL). The differential buffer can drive out LVDS,
mini-LVDS, and RSDS signaling levels. The serializer takes up to 10 bits wide parallel
data from the FPGA core, clocks it into the load registers, and serializes it using shift
registers clocked by the left or right PLL before sending the data to the differential
buffer. The most significant bit (MSB) of the parallel data is transmitted first.
The load and shift registers are clocked by the load enable (load_en) signal and the
diffioclk (clock running at serial data rate) signal generated from PLL_Lx (left
PLL) or PLL_Rx (right PLL). The serialization factor can be statically set to ×4, ×6, ×7,
×8, or ×10 by using the Quartus II software. The load enable signal is derived from the
serialization factor setting. Figure 8–3 is a block diagram of the HardCopy IV
transmitter.
Figure 8–3. HardCopy IV Transmitter
10
Internal
Logic
Serializer
TX_OUT
PLL_Lx /
PLL_Rx
diffioclk
load_en
The HardCopy IV transmitter data channel can be configured to generate a source
synchronous transmitter clock output, allowing you to place the output clock near the
data outputs to simplify board layout and reduce clock-to-data skew. Different
applications often require specific clock-to-data alignments or specific data rate to
clock rate factors. The transmitter can output a clock signal at the same rate as the
data. Depending on the serialization factor, the output clock can also be divided by a
factor of 2, 4, 8, or 10. You can set the phase of the clock in relation to the data at 0° or
180° (edge or center aligned). The left and right PLLs (PLL_Lx and PLL_Rx) provide
additional support for other phase shifts in 45° increments. These settings are made
statically in the Quartus II MegaWizard^™ Plug-In Manager. Figure 8–4 shows the
HardCopy IV transmitter in clock output mode.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation