HC4GX15 Datasheet, PDF (332/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–68
Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
Figure 1–54. Clock and Data Recovery Unit
rx_locktorefclk
rx_locktodata
signal detect
rx_freqlocked
rx_datain
LTR/LTD
Controller
Phase ^Down
Detector Up
(PD)
rx_cruclk /1, /2, /4
/2
Phase
Frequency
Detector
(PFD)
Up
Down
Clock and Data Recovery (CDR) Unit
High-Speed
Recovered Clock
Low-Speed
/2
Recovered Clock
Charge Pump
+
Loop Filter
V_CO
/L
rx_pll_locked
/M
The CDR operates either in LTR mode or LTD mode. In LTR mode, the CDR tracks the
input reference clock. In LTD mode, the CDR tracks the incoming serial data.
After the receiver power up and reset cycle, the CDR must be kept in LTR mode until
it locks to the input reference clock. Once locked to the input reference clock, the CDR
output clock is trained to the configured data rate. The CDR can now switch to LTD
mode to recover the clock from incoming data. The LTR/LTD controller controls the
switch between LTR and LTD modes.
Lock-to-Reference Mode
In LTR mode, the phase frequency detector in the CDR tracks the receiver input
reference clock, rx_cruclk. The PFD controls the charge pump that tunes the VCO
in the CDR. Depending on the data rate and the selected input reference clock
frequency, the Quartus II software automatically selects the appropriate /M and /L
divider values such that the CDR output clock frequency is half the data rate. An
active high, the rx_pll_locked status signal is asserted to indicate that the CDR has
locked to phase and frequency of the receiver input reference clock. Figure 1–55
shows active blocks when CDR is in LTR mode.
1 The phase detector (PD) is inactive in LTR mode.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation