HC4GX15 Datasheet, PDF (285/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–21
Transceiver Port List
Table 1–2. HardCopy IV GX ALTGX Megafunction Ports (Part 14 of 14)
Port Name
rx_pipedatavalid
pipeelecidle
Input/Output
Description
Output
Valid data and control on the rx_dataout
and rx_ctrldetect ports indicator.
Functionally equivalent to the rxvalid signal
defined in the PIPE specification revision 2.0.
Output
Electrical idle detected or inferred at the
receiver indicator. This feature is functionally
equivalent to the rxelecidle signal defined
in the PCI Express (PIPE) specification revision
2.0. If the electrical idle inference block is
enabled, it drives this signal high when it infers
an electrical idle condition, as described in
“Electrical Idle Inference” on page 1–136.
Otherwise, it drives this signal low. If the
electrical idle inference block is disabled, the
rx_signaldetect signal from the signal
detect circuitry in the receiver buffer is inverted
and driven on this port.
Asynchronous signal.
Reset and Power Down
gxb_powerdown
rx_digitalreset
rx_analogreset
tx_digitalreset
Input
Input
Input
Input
Transceiver block power down. When asserted
high, all digital and analog circuitry within the
PCS, PMA, CMU channels, and the CCU of the
transceiver block is powered down.
Asserting the gxb_powerdown signal does
not power down the REFCLK buffers.
Asynchronous signal. The minimum pulse
width is 1 μs (pending characterization).
Receiver PCS reset. When asserted high, the
receiver PCS blocks are reset. The minimum
pulse width is two parallel clock cycles.
Receiver PMA reset. When asserted high,
analog circuitry within the receiver PMA gets
reset. The minimum pulse width is two parallel
clock cycles.
Transmitter PCS reset. When asserted high, the
transmitter PCS blocks are reset. The minimum
pulse width is two parallel clock cycles.
Calibration Block
cal_blk_clk
cal_blk_powerdown
Input
Input
Clock for transceiver calibration blocks.
Calibration block power down control.
Scope
Channel
Channel
Transceiver
block
Channel
Channel
Channel
Device
Device
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3