HC4GX15 Datasheet, PDF (409/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–145
As a result of the signaling rateswitch between Gen1 (2.5 Gbps) and Gen2 (5 Gbps),
the core fabric-transceiver interface clock switches between 125 MHz and 250 MHz.
The core fabric-transceiver interface clock clocks the read side and write side of the
transmitter phase compensation FIFO and the receiver phase compensation FIFO of
all bonded channels, respectively. It is also routed to the core fabric on a global or
regional clock resource and looped back to clock the write port and read port of the
transmitter phase compensation FIFO and the receiver phase compensation FIFO,
respectively. Due to the routing delay between the write and read clock of the
transmitter and receiver phase compensation FIFOs, the write pointers and read
pointers might collide during a rateswitch between 125 MHz and 250 MHz. To avoid
collision of the phase compensation FIFO pointers, the PCI Express (PIPE) rateswitch
controller automatically disables and resets the phase compensation FIFO pointers of
all bonded channels during clock switch. When the PIPE clock switch circuitry in the
local clock divider indicates successful clock switch completion, the PIPE rateswitch
controller releases the phase compensation FIFO pointer resets.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3