HC4GX15 Datasheet, PDF (445/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–181
Figure 1–151 shows the ALTGX transceiver datapath when configured in Serial
RapidIO mode.
Figure 1–151. Serial RapidIO Mode Datapath
Core
Fabric
TX Phase
Compensation
FIFO
wrclk rdclk
Transmitter Channel PCS
Byte
Serializer
8B/10B
Encoder
tx_coreclk[0]
tx_clkout[0]
Core
Fabric-Transceiver
Interface Clock
RX Phase
Compensation
FIFO
Byte
De-
Serializer
/2
8B/10B
Decoder
Low-Speed Parallel Clock
Receiver Channel PCS
Rate
Match
FIFO
Word
Aligner
Transmitter Channel PMA
Serializer
High-Speed Serial Clock
Local
Clock Divider
Receiver Channel PMA
De-
CDR
Serializer
rx_coreclk[0]
Parallel Recovered Clock
/2
Low-Speed Parallel Clock
HardCopy IV GX transceivers, when configured in Serial RapidIO functional mode,
provide the following PCS and PMA functions:
■ 8B/10B encoding/decoding
■ Word alignment
■ Lane synchronization state machine
■ Clock recovery from the encoded data
■ Serialization/deserialization
1 HardCopy IV GX transceivers do not have built-in support for other PCS functions;
for example, pseudo-random idle sequence generation and lane alignment in 4×
mode. Depending on your system requirements, you must implement these functions
in the logic array or external circuits.
Synchronization State Machine
In Serial RapidIO mode, the ALTGX MegaWizard Plug-In Manager defaults the word
alignment pattern to K28.5. The word aligner has a synchronization state machine that
handles the receiver lane synchronization.
The ALTGX MegaWizard Plug-In Manager automatically defaults the
synchronization state machine to indicate synchronization when the receiver receives
127 K28.5 (10'b0101111100 or 10'b1010000011) synchronization code groups without
receiving an intermediate invalid code group. Once synchronized, the state machine
indicates loss of synchronization when it detects three invalid code groups separated
by less than 255 valid code groups or when it is reset.
Receiver synchronization is indicated on the rx_syncstatus port of each channel. A
high on the rx_syncstatus port indicates that the lane is synchronized and a low
indicates that it has fallen out of synchronization.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3