HC4GX15 Datasheet, PDF (529/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
2–71
Description of Transceiver Channel Reconfiguration Modes
3. In the Option box of the More Fitter Settings page, set the Generate GXB
Reconfig MIF option to On based on the dynamic reconfiguration mode enabled
(Figure 2–34).
Figure 2–34. Step 3 to Enable .mif Generation
The .mif is generated in the Assembler stage of the compilation process. However, for
any change in the design or the above settings, the Quartus II software runs through
the fitter stage before starting the assembler stage.
Reusing .MIFs
To configure the transceiver PLLs and receiver PLLs for multiple data rates, it is
important to understand the input reference clock requirements. This helps you to
efficiently create the clocking scheme for reconfiguration and to reuse the .mifs across
all channels in the device. This section reviews the new clocking enhancements and
the implications of using input clocks from various clock sources.
The available clock inputs appear as a pll_inclk_rx_cruclk[] port and can be
provided from the inter-transceiver block lines (also known as Inter Quad [IQ] lines),
from the global clock networks that are driven by an input pin, or by a PLL cascade
clock.
1 For more information about input reference clocking, refer to the Input Reference
Clocking section of the Stratix IV Transceiver Clocking chapter of volume 2 of the Stratix
IV Device Handbook.
The following section describes the clocking requirements to reuse .mifs.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3