HC4GX15 Datasheet, PDF (12/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Features
Chapter 1: HardCopy IV Device Family Overview
Features
HardCopy IV devices offer the following features:
■ General
■ Fine-grained HCell architecture resulting in a low-cost, high-performance,
low-power ASIC
■ Fully tested production-quality samples typically available 14 weeks from the
date of your design submission
■ Design functionality the same as the Stratix IV FPGA prototype
■ System performance and power
■ Core logic performance up to double that of the Stratix IV FPGA prototype
■ Power consumption reduction of typically 50% from the Stratix IV FPGA
prototype
■ Robust on-chip hot socketing and power sequencing support
■ Support for instant-on or instant-on-after-50 ms power-up modes
■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for
robust signal integrity
1 The actual performance and power consumption improvements described
in this data sheet are design-dependent.
■ Transceivers (HardCopy IV GX family)
■ Up to 36 full-duplex CDR-based transceivers in HardCopy IV GX devices
supporting data rates up to 6.5 Gbps
■ Dedicated circuitry to support physical layer functionality for popular serial
protocols, such as PCI Express (PIPE) Gen1 and Gen2, Gigabit Ethernet, Serial
RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre
Channel, SFI-5, and Interlaken
■ Complete PCI Express (PIPE) protocol solution with embedded PCI Express
hard IP blocks that implement PHY-MAC layer, Data Link layer, and
Transaction layer functionality
■ Programmable transmitter pre-emphasis and receiver equalization circuitry to
compensate for frequency-dependent losses in the physical medium
■ Typical physical medium attachment (PMA) power consumption of 100 mW at
3.125 Gbps and 135 mW at 6.375 Gbps per channel
■ Logic and Digital Signal Processing (DSP)
■ 3.8 to 15 million usable gates for both logic and DSP functions (as shown in
Table 1–1)
■ High-speed DSP functions supporting 9 × 9, 12 × 12, 18 × 18, and 36 × 36
multipliers, multiple accumulate functions, and finite impulse response (FIR)
filters
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation