HC4GX15 Datasheet, PDF (134/668 Pages) Altera Corporation – HardCopy IV Device Handbook

8–24
Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
Design Recommendations
Figure 8–24. Both Center Left/Right PLLs Driving Cross-Bank DPA-Disabled Channels
Simultaneously
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
Reference
CLK
Center
Left/Right PLL
Center
Left/Right PLL
Reference
CLK
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
Design Recommendations
To implement the high-speed differential interface successfully, Altera recommends
that you follow these design guidelines:
1. Altera provides HardCopy IV IBIS models to verify I/O timing and
characteristics. Altera strongly recommends you verify the I/O interfaces with
simulation before you submit the design to the HardCopy Design Center.
f For more information about signal integrity simulations with third-party tools, refer
to the Signal Integrity Analysis with Third-Party Tools chapter in volume 3 of the
Quartus II Handbook.
2. You can use center PLLs for both Tx and Rx, but corner PLLs are preferred for Tx
applications over Rx applications.
3. Altera recommends you share the lvdsclk and load_en signals between
transmitting and receiving channels in the same I/O bank whenever possible.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation