HC4GX15 Datasheet, PDF (655/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: DC and Switching Characteristics of HardCopy IV Devices
1–25
Switching Characteristics
Table 1–26. HardCopy IV PLL Specifications—Preliminary (Part 2 of 2) (Note 1)
Symbol
Parameter
Min Typ
Max
Unit
f_DRIFT
Frequency drift after PFDENA is disabled for duration of 100 us — —
±10
%
Notes to Table 1–26:
(1) Pending silicon characterization.
(2) This specification is limited in Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(3) This specification is limited by the lower of the two: I/O FMAX or FOUT of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less
than 200 ps.
(5) Peak-to-peak jitter with a probability level of 10^–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–38.
(6) High bandwidth PLL settings are not supported in external feedback mode.
DSP Block Specifications
Table 1–27 describes the HardCopy IV DSP block performance specifications.
Table 1–27. HardCopy IV DSP Block Performance Specifications—Preliminary (Note 1), (2)
Mode
Number of
Multipliers
Max
Unit
9×9-bit multiplier
1
410
MHz
12×12-bit multiplier
1
410
MHz
18×18-bit multiplier
1
495
MHz
36×36-bit multiplier
1
365
MHz
18×18-bit multiply accumulator
4
390
MHz
18×18-bit multiply adder
4
405
MHz
18×18-bit multiply adder-signed full precision
2
405
MHz
18×18-bit multiply adder with loopback (3)
2
405
MHz
36-bit shift (32 bit data)
1
390
MHz
Double mode
1
365
MHz
Notes to Table 1–27:
(1) Maximum is for fully pipelined block with Round and Saturation disabled.
(2) Pending silicon characterization.
(3) Maximum is for non-pipelined block with loopback input registers disabled and Round and Saturation
disabled.
TriMatrix Memory Block Specifications
Table 1–28 describes the HardCopy IV TriMatrix memory block specifications.
Table 1–28. HardCopy IV TriMatrix Memory Block Performance Specifications—Preliminary (Part 1
of 2) (Note 1)
Memory
Mode
TriMatrix
Memory
Max
Unit
Single port 64×10
1
500
MHz
MLAB
Simple dual-port 32×20 single clock
1
500
MHz
Simple dual-port 64×10 single clock
1
500
MHz
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 4